ESP8266 breadboard adapter

ESP-Breakout1-1024x683

The rise of the ESP8266 WiFi chip was almost overnight with Espressif’s open approach and pushing from Hackaday. While no ground-breaking product has yet emerged, the development on the chip are phenomenon.The ESP8266 modules manufacture seems to prefer non-standard 2.0mm pitch connector.

The modules are ESP-07 and ESP-12, both having identical pinout but only differ in antenna type.They choose these two because they have all the I/O available, and using same edge castellation (half vias) connectors which is easy to work with.x

The modules are 16mm tall, easily occupies 4 rows (2 rows on each side) on a breadboard. Therefore they  first design requirement is to minimize real estate on the breadboard. To do this they  made some custom pin headers by modifying from SMT pin header.

Removed pair of pins from both ends and replace with through hole pins. This little touch strengthens the bounding between pin header and the board. With this design, they maintain 4 rows occupation on the breadboard, that leaves another 6 rows for wiring.

The boot mode of ESP-8266 is often another source of confusion. The table below summarizes different boot modes during power on or reset:

Boot Mode CH_PD GPIO15 GPIO0
Run firmware High Low HiZ (Internal P-UP)
Flash firmware High Low Low

In firmware flashing mode, user is able to update new firmware from UART0 using FLASH_DOWNLOAD_TOOLS or esptool.py.

During idle state, internal pull-up in the ESP8266 RESET pin turns on Q1. Q2 cut off so GPIO0 remains high due to GPIO0 internal pull-up. At the same time, C1 discharges from R2 and Q1. When user presses SW1, RESET goes low immediately. Meanwhile, Q1 turns off and 3.3V power charges C1 through R1 and R2. If user releases SW1 quickly and the voltage across C1 has not reached Q2?s threshold voltage, Q2 remains off and ESP8266 enters normal running mode. However if user holds SW1 long enough before releasing, Q2 will turn on, pull GPIO0 low. At the moment user releases SW1, RESET goes high but GPIO0 will be held low for a while due to C1 have to discharge through R2 and Q1. The choice of C1 and R2 are such that it keeps GPIO0 low long enough for ESP8266 to enter program mode.

The board also includes a 3.3V LDO (AMS-1117 3.3) and a UART header using FTDI Basic pin out.

ESP8266-breakout-in-action

Source :ba0sh1.com

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